Department Events
COMPUTER ORGANIZATION AND ARCHITECTURE
The course will enable the students to
- Learn the binary arithmetic and working of various digital circuits used in computer and basic structural design.
- Register Transfer Language, Control Unit, CPU etc.
- Learn how all-arithmetic operations are done at architecture level.
Course Outcomes (COs):
Course Outcome (at course level) | Learning and teaching strategies | Assessment Strategies |
|---|---|---|
The students will: CO52. Explain the design of the various functional units and digital components of computers. CO53. Compare register transfers and micro operations used in computer architecture CO54. Identify the elements of modern instructions sets and their impact on processor design. CO55. Examine the function of each element of a memory hierarchy, CO56. Identify and compare different methods for computer I/O. | Approach in teaching: Interactive Lectures, Discussion, Tutorials, Reading assignments, Demonstration
Learning activities for the students: Self-learning assignments, Effective questions, Seminar presentation, Giving tasks | Class test, Semester end examinations, Quiz, Solving problems in tutorials, Assignments, Presentation |
Basic Gates, Basic laws of Boolean algebra, Simplification of Boolean algebra. Combinational Logic Design: Standards representation for logical expression, Minimization of logical functions in terms of Maxterm and Minterm, Simplifications of Boolean equations using K-maps, don’t care conditions.
Arithmetic Circuits: Half Adder, Full Adder, Half Subtractor, Full Subtractor, Parallel Binary Adder (IC 7483), Parallel binary Subtractor, Parallel binary adder/Subtractor. Multiplexers (74151/74150), De-Multiplexers (74154), decoders (74139/74154/7445), encoders (Octal to binary, decimal to BCD, priority), BCD to Seven segment decoder
Sequential Logic: Sequential circuits: Flip-flops, S-R, D, J-K, T, Clocked Flip-flop, Race around condition, Master slave Flip-Flop (truth tables, working)
Register Transfer Language, Register transfer, Bus and Memory transfer, Arithmetic Micro- operations, Logic Micro-operations, Shift Micro-operations, Arithmetic Logic Shift Unit.
Instruction Codes, Computer Registers: Common bus system; Computer Instructions: Instruction formats; Instruction Cycle: Fetch and Decode, Flowchart for Instruction cycle; Register reference instructions. I/O & Interrupt, types of Interrupts, Interrupt cycle. Central Processing Unit: Introduction, General Register Organization, Stack Organization: Register stack, Memory stack; Instruction Formats, Addressing Modes
Memory Hierarchy, Main Memory, Auxiliary Memory, Associative Memory, Cache Memory, Virtual Memory. Multiprocessors: Characteristics of multi-processors inter connection structure; inter processor arbitration, inter-processor communication and synchronization.
REFERENCES:
1. William Stallings, “Computer Organization and Architecture”, 4th Edition, Prentice Hall of India Private Limited, 2001.
2. Malvino, Brown, “Digital Computer Electronics: An Introduction to Microcomputers”, 3rd edition, McGraw Hill, 1993.
3. Moris Mano, “Digital Logic and Computer Design”, PHI Publications, 2002.
4. Malvino Leach, "Digital Principles and Application", Mc Graw Hill Publications.
5. Malvino, “Digital Computer Electronics”, Mc Graw Hill Publications.
E-RESOURCE
1. https://www.tutorialspoint.com/computer_logical_organization/boolean_algebra.htm
2. http://staff.ustc.edu.cn/~csli/graduate/algorithms/book6/chap29.htm
3. https://vardhaman.org/wp-content/uploads/2021/03/CAO-Unit-I-part-3.pdf
4. https://www.pvpsiddhartha.ac.in/dep_it/lecture%20notes/Computer%20System%20Architecture/unit2.pdf
5. http://vemu.org/uploads/lecture_notes/30_12_2019_1655081181.pdf
JOURNALS:
1. https://www.researchgate.net/publication/334054812_Boolean_Algebra_and_Logic_Gates
2. https://www.sciencedirect.com/topics/engineering/central-processing-unit
3. Journal of the Brazilian Computer Society, SpringerOpen
4. Journal of Internet Services and Applications, SpringerOpen
