COMPUTER ORGANIZATION AND ARCHITECTURE

Paper Code: 
CBCA 202
Credits: 
03
Periods/week: 
03
Max. Marks: 
100.00
Objective: 

In this module, students will learn the binary arithmetic and working of various digital circuits used in computer and basic structural design, Register Transfer Language, Control Unit, CPU etc. They will also learn how all-arithmetic operations are done at architecture level. It also explains the basic organization of Memory and I/O devices.

9.00
Unit I: 
Boolean Algebra and Logic Gates

Basic Gates, Basic laws of Boolean algebra, Simplification of Boolean algebra. Combinational Logic Design: Standards representation for logical expression, Minimization of logical functions in terms of Maxterm and Minterm, Simplifications of Boolean equations using K-maps, don’t care conditions.

9.00
Unit II: 
Arithmetic Circuits

Arithmetic Circuits: Half Adder, Full Adder, Half Subtractor, Full Subtractor, Parallel Binary Adder(IC 7483), Parallel binary Subtractor,  Parallel binary adder/Subtractor. Multiplexers (74151/74150), De-Multiplexers (74154), decoders (74139/74154/7445), encoders (Octal to binary, decimal to BCD, priority), BCD to Seven segment decoder

Sequential Logic: Sequential circuits: Flip-flops, S-R, D, J-K, T, Clocked Flip-flop, Race around condition, Master slave Flip-Flop (truth tables, working)

9.00
Unit III: 
Overview Of Register Transfer And Micro operations

Register Transfer Language, Register transfer, Bus and Memory transfer, Arithmetic Micro-operations, Logic Micro-operations, Shift Micro-operations, Arithmetic Logic Shift Unit.

9.00
Unit IV: 
Basic Computer Organization And Design

Instruction Codes, Computer Registers: Common bus system; Computer Instructions: Instruction formats; Instruction Cycle: Fetch and Decode, Flowchart for Instruction cycle; Register reference instructions. I/O & Interrupt, types of Interrupts, Interrupt cycle. Central Processing Unit: Introduction, General Register Organization, Stack Organization: Register stack, Memory stack; Instruction Formats, Addressing Modes

9.00
Unit V: 
Memory Organization

Memory Hierarchy, Main Memory, Auxiliary Memory, Associative Memory, Cache Memory, Virtual Memory. Multiprocessors: Characteristics of multi-processors inter connection structure; inter processor arbitration, inter-processor communication and synchronization.

ESSENTIAL READINGS: 
  1. Morris Mano, “Computer System Architecture”, 3rd Edition, Prentice-Hall of India Private Limited, 1999.
  2. R. P. Jain, “Modern Digital Electronics”, Mc Graw Hill Publising Company limited.
  3. S. Salivahanan & S. Arivyhgan, “Digital circuits and design”,”Vikas Publishing house Pvt.Ltd.
  4. V.K. Mehta, “Principles of Electronics”, Fifth Edition, S. Chand & Co.
REFERENCES: 
  1. William Stallings, “Computer Organization and Architecture”, 4th Edition, Prentice Hall of India Private Limited, 2001.
  2. Malvino, Brown, “Digital Computer Electronics: An Introduction to Microcomputers”, 3rd edition, McGraw Hill, 1993.
  3. Moris Mano, “Digital Logic and Computer Design”, PHI Publications, 2002.
  4. Malvino Leach, "Digital Principles and Application", Mc Graw Hill Publications.
  5. Malvino, “Digital Computer Electronics”, Mc Graw Hill Publications.
Academic Year: 
2019-20
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