The course will enable the students to
Course | Learning Outcome (at course level) | Learning and teaching strategies | Assessment Strategies | |
Course Code | Course Title | |||
24CBCA 202
| Computer Organization and Architecture (Theory)
| CO61. Design logic circuits by applying the fundamental principles of Boolean algebra. CO62. Apply theoretical concepts of digital circuit design to solve circuit- specific applications. CO63. Compare register transfers and micro operations used in computer architecture. CO64. Identify the elements of modern instructions sets and their impact on processor design. CO65. Examine the function of each element of a memory hierarchy. CO66. Contribute effectively in course- specific interaction. | Approach in teaching: Interactive Lectures, Discussion, Reading assignments, Demonstration
Learning activities for the students: Self-learning assignments, Effective questions, Seminar presentation. | Class test, Semester end examinations, Quiz, Assignments, Presentation |
Basic Gates, Basic laws of Boolean algebra, Simplification of Boolean algebra. Combinational Logic Design: Standards representation for logical expression, Minimization of logical functions in terms of Maxterm and Minterm, Simplifications of Boolean equations using K-maps, don’t care conditions.
Arithmetic Circuits: Half Adder, Full Adder, Half Subtractor, Full Subtractor, Parallel Binary Adder (IC 7483), Parallel binary Subtractor, Parallel binary adder/Subtractor. Multiplexers (74151/74150), De-Multiplexers (74154), decoders (74139/74154/7445), encoders (Octal to binary, decimal to BCD, priority), BCD to Seven segment decoder
Sequential Logic: Sequential circuits: Flip-flops, S-R, D, J-K, T, Clocked Flip-flop, Race around condition, Master slave Flip-Flop (truth tables, working)
Register Transfer Language, Register transfer, Bus and Memory transfer, Arithmetic Micro- operations, Logic Micro-operations, Shift Micro-operations, Arithmetic Logic Shift Unit.
Instruction Codes, Computer Registers: Common bus system; Computer Instructions: Instruction formats; Instruction Cycle: Fetch and Decode, Flowchart for Instruction cycle; Register reference instructions. I/O & Interrupt, types of Interrupts, Interrupt cycle. Central Processing Unit: Introduction, General Register Organization, Stack Organization: Register stack, Memory stack; Instruction Formats, Addressing Modes
Memory Hierarchy, Main Memory, Auxiliary Memory, Associative Memory, Cache Memory, Virtual Memory. Multiprocessors: Characteristics of multi-processors inter connection structure; inter processor arbitration, inter-processor communication and synchronization.
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